A next-generation electronic product is asked to have multiple functions and high-speed performance other than compactness. The integrated-circuit manufacturers have moved to smaller design rules to make chips with much more electronic devices. On the other hand, the techniques for packaging the chips or semiconductor substrates have also been developed for the same purpose.
Conventionally, a flip-chip chip size package (FCCSP) substrate 10 used to construct the so-called “molded interconnection substrate (MIS)” can be illustrated in FIG. 1. A photo-sensitive primer material can be used in the formation of the dielectric material layer 17 on the molding compound layer 16, so it is required to have a high resolution of photolithography in microfabrication. Especially for the package manufacturing process of fine pitch, the primer material is expensive and restricted to some specific chemical compositions. Moreover, the metal pillar which connects the upper-layer conductive wires 14 and the lower-layer conductive wires 12 of the package substrate 10 includes two segments 18 and 19. These two segments 18 and 19 of metal pillar should be aligned vertically. However, they are respectively formed in different photolithography processes of the molding compound layer 16 and the dielectric material layer 17 in the existing FCCSP fabrication, so there may be location deviations between the two segments 18 and 19 caused by the possible photo-mask misalignments among the photolithography processes. Also, the affinity between the primer material and either the metal pillar or the molding compound may not strong enough. These may make yield rate and reliability of the product worse. Therefore, it is in need to develop a new means for fabricating package substrates.